Design and VLSI Implementation of High Performance NCO Based on Galois Fields

摘要：

In this paper, a novel NCO architecture is presented. The error-free computational property of Galois fields is used to improve the NCO performance, which is commonly restricted by the phase truncation effect in the traditional sine look-up table based architecture. Compared with the conventional digital oscillator, the frequency switching time of our design is reduced largely, which makes it attractive candidate for applications that require fast and phase-continuous frequency switching. The SFDR of the architecture is 75dB with 10-bit phase resolution and 12-bit amplitude resolution. The Verilog RTL is simulated and verified to work at 240 MHz in a 2V3000FG676-6 Xilinx Virtex2 FPGA.

作者: Jinkai Long Xiaoxin Cui Dunshan Yu

作者单位: Institute of Microelectronics, Peking University, Beijing 100871, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 245-247

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）