Digital Background Calibration of MDAC Stage Gain Error and DAC Error in Pipelined ADC

摘要：

A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudorandom sequences into the MDAC. With this method, not only small capacitors* might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined ADC could be replaced by low gain low power counterparts, which results in improving the figure-of-merit (FOM) significantly. A 12-bit 100MS/s pipelined ADC achieves 11.934 bits ENOB and 101.22dB SFDR, compared with 7.685 bits and 50.95dB without calibration.

作者: Shuying Zhang Ling Ding Jiajing Xu Fuquan Zhang Shuai Wang Yuchun Chang

作者单位: State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, J State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, J

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 251-253

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）