A Random Delay Design of Processor against Power Analysis Attacks

摘要：

As an important implementation of Cryptographic algorithm, processor should be thought about the ability of resistant power attack. In this paper we show a processor architecture, which automatically detects the execution of the encryption algorithms, and interleaves the execution of cryptographic algorithm code with that of dummy instructions to reduce the correlations between the leakage and the inside operations, and thus make the statistic analysis infeasible. Experiment verifies the efficiency of the proposed method.

关键词： processor random instruction injection power analysis design technique

作者: Hongfei Qu Jinfu Xu Yingjian Yan

作者单位: Zhengzhou Institute of information technology, Zhengzhou 450004, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 254-256

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）