An Improved High Gain and Wide Bandwidth Operational Amplifier for the SHA Circuit in a Pipelined ADC

摘要：

This paper presents a high gain and wide bandwidth fully differential operational amplifier (op amp) used in a sample and hold amplifier (SHA) circuit for a 12bit, 50Ms/s pipelined ADC. The gain-boosted technique is adopted to achieve a high gain without reduction of the output swing, while a new frequency compensation method is developed to compensate the bandwidth degradation caused by the gain-boosted structure. Simulation results show that the amplifier exhibits a gain of U4dB, unity gain bandwidth of 721 MHz, and 2V output range from a single 3.3V supply. A sample and hold circuit employing the amplifier is implemented in a commercial 0.35um CMOS process, the measurement results show that the amplifier should meet the requirement for the pipelined ADC operating at up to 50MHz sampling clock.

作者: Yu Wang Hai-gang Yang Zhen-hua Ye Hui Zhang Fei Liu

作者单位: Institute of Electronic, Chinese Academy of Science(CAS),Beijing 100190, China Graduate University o Institute of Electronic, Chinese Academy of Science(CAS),Beijing 100190, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 269-271

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）