A Multithreaded Processor Core with Low Overhead Context Switch for IP-packet Processing
In this paper a multithreaded processor with hardware context switch mechanism driven by external events is presented for multi-processor system on chip (MPSoC). Combining this mechanism with asynchronous memory access the proposed processor implements Nonpreemptive thread scheduling which can assure fairness of threads and optimization for single thread. The overhead of hardware thread switch is reduced to 0-1 clock cycle with this structure. Proposed multithreaded processor is designed based on 5 stages pipeline RISC processor in order for easier realization. FPGA simulation results show that the whole performance of the proposed structure improves about 3.8 times than the baseline one with area increased only 7％. It shows perfect performance/area ratio.
Kang Li Hong Zhang Jiandong Li Yue Hao Yuanbin Xie
School of Microelectronics, Xidian University, Xian 710071, China The State Key Lab. of ISN, Xidian University, Xian 710071, China
国际会议
上海
英文
272-274
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）