A Fully Programmable Frame Synchronization Architecture of OFDM Systems Implemented on a Multi-Core Processor Platform

摘要：

This paper presents a fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform. By utilizing the guard interval in OFDM signals, the coarse symbol synchronization (CSS) and the fractional carrier frequency offset estimation (CFO) are considered simultaneously. The multi-core processor platform is a 2-Dimension mesh array of SIMD (Single Instruction Multiple Data) cores, and is well suited for digital communication applications. By exploring the task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access, and route-lengthminimized task mapping techniques, the implementation can achieve a throughput up to 224Mbps, which shows the great advantage of multi-core processor platform.

作者: Wenhua Fan Bei Huang Jialin Cao Yun Chen Zhiyi Yu Xiaoyang Zeng

作者单位: State Key Lab of ASIC and System, Fudan University, Shanghai 201203, P.R.China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 278-280

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）