A 200MS/S 10-bit Current-steering D/A Converter with On-chip Testbench

摘要：

This paper presents a 10-bit 200MS/s CMOS currentsteering digital-to-analog converter (DAC) with onchip testbench. The proposed DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. The measurement results show that the converter achieves a spurious-free dynamic range (SFDR) up to 78.7dBc. The full-scale output current is 20mA with 3V power supply for analog part, while the digital part of the chip operates at 1.8V. The DNL and INL are less than 0.07LSB and 0.15LSB respectively due to an improved current switching scheme. The active area of DAC core is 0.2 mm in a standard 1P-6M 0.18μm CMOS process.

作者: Shaopeng Wang Yannan Ren Changyi Yang Fule Li Zhihua Wang

作者单位: Institute of Microelectronics of Tsinghua University, Beijing, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 296-298

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）