Digitally-Assisted Sample-to-Sample Jitter Correction in ADC Systems
In this paper we present a technique that permits the correction of errors caused by the timing jitter associated with sampling clocks cadencing analog-todigital converters (ADCs). The correction system is digital, completely independent of the front-end ADC and corrects the data out of the converter on a sample-to-sample basis. Relative to the ADC under consideration, the proposed technique enables quasizero jitter sampling characteristics which is demonstrated experimentally in this paper.
Mourad Oulmane Gordon W. Roberts
Integrated Microsystems Laboratory, McGill University 3480 University Street, Montreal, Quebec, CANADA H3A 2A7
国际会议
上海
英文
302-305
2010-11-01(万方平台首次上网日期,不代表论文的发表时间)