Design and Verification of Distributed RAM Using Look-Up Tables in an SOI-Based FPGA

摘要：

A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5 urn SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement Block RAM in implementing the data storage logic of many applications. The functionality and performance of the Distributed RAM have been proven in our test circuit. Comparing with the published data on the Distributed RAM in Xilinx Spartan FPGA, our Distributed RAM average access time has about 21％ improvement.

作者: Xiaowei Han Stanley L. Chen Lihua Wu Yan Zhao Yan Li

作者单位: Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, P.R. China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 306-308

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）