A 14-bit 100 MS/s Self-Calibrated DAC With a Randomized Calibration-Period

摘要：

A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background selfcalibration technique with a randomized calibrationperiod is adopted to improve the dynamic performance. The DAC is fabricated in SMIC 0.13-μm CMOS process and occupies a 1.29mm2 die area. The measured DNL/INL is better than 3.1LSB/4.3LSB. The SFDR is 72.8dB at 1 MHz signal and 100 MHz sampling frequency. And the current consumption is 50mA under 1.2/3.3V dual power supplies for digital and analog part, respectively.

作者: Dong Qiu Sheng Fang Renzhong Xie Ran Li Ting Yi Zhiliang Hong

作者单位: State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 312-314

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）