Low-latency SDRAM Controller for Shared Memory in MPSoC

摘要：

In a memory structure shared by multiple processors based on Multiprocessor Systems on Chip (MPSoC), the efficiency of memory bus access becomes the bottleneck of the overall system efficiency. This paper presents a low-latency SDARM controller structure integrated in MPSoC, which controls the off-chip SDRAM memory. Consecutive same row optimization and odd-even bank optimization are used to eliminate precharge time and active to read/write execution in mempry access. Burst mode supported by data transmit block improves the efficiency of the memory bus. Simulation results show that memory performance improves maximally by 56％ compared to pre-optimized, making it. meet the high throughput requirements of shared-memory controller in MPSoC.

作者: Pei-Jun Ma Jia-Liang Zhao Kang Li Ling-Fang Zhu Jiang-Yi Shi

作者单位: Key Laboratory of Wide Band-gap Semiconductor Materials and Devices of Ministry of Education, School of Microelectronics, Xidian University, Xian 710071, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 321-323

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）