The Application and Optimization of SDRAM Controller in Multicore Multithreaded SoC

摘要：

An integrated SDRAM controller with asynchronous access architecture is proposed. The controller takes charge of data transfer between off-chip SDRAM memory and the multicore multithreaded processors. The interleaving optimization for opposite bank is incorporated into the SDRAM controller, which can reduce memory latency and improve the memory bus performance. FPGA results show that the proposed controller reduces execution time by up to 48％ than the original structure and improves the throughput of SDRAM data bus by 29％.

作者: Pei-Jun Ma Ling-Fang Zhu Kang Li Jia-Liang Zhao Jiang-Yi Shi

作者单位: Key Laboratory ofWide Band-gap Semiconductor Materials and Devices of Ministry of Education School of Microelectronics, Xidian University, Xian 710071, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 324-326

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）