A Novel and Simple 0.18μm CMOS Sub-1V Low-Dropout Regulator

摘要：

A CMOS capacitor-free low-dropout (LDO) voltage regulator with 0.65-1.8V power supply is presented. Positive feedback is used to build the differential computation of the error amplifier and the positive feedback gain is less than unity to ensure the stability. The LDO is designed in TSMC 0.18μm CMOS processes. The maximum output current of the LDO is 50mA at an output of 0.5V. The simulation results show the average settling time of 9.9us can be achieved with 0.5％ error for load current change between 5mA and 50mA, and the line and load regulations are 0.847％/V and 22.8ppm/mA, respectively.

关键词： Low dropout voltage regulator positive feedback capacitor free

作者: Zhi-Meng Wu Quan-Yuan Feng Qian-Yin Xiang

作者单位: Institute of Microelectronics, Southwest Jiaotong University, Chengdu 610031, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 357-359

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）