Enhance up to 40％ Performance of SH-4A processor by using Prefix instruction

摘要：

Instruction set development is an effective way to improve processor performance. In SH-4A core enhancement, Prefix instruction is introduced as a technique to enrich function of original instruction. As a result, we have successfully integrated 130 new 32-bit instructions to 16-bit original instruction set and performance of new core is improved up to 43％ compared to conventional model.

作者: Hung Bao Vo Y Thien Vo Dat Duy Nguyen Huong Thien Hoang Yoichi Yuyama Hirofumi Nishi Masayuki Ito

作者单位: Renesas Design Vietnam Co., Ltd, Tan Thuan Road, Tan Thuan Processing Zone, Dist.7, Ho Chi Minn City Renesas Electronics Corp., 5-20-1, Josuibon-cho, Kodaira, Tokyo, 187-8588, Japan

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 360-362

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）