A 65nm Adaptive Bandwidth Clock Generator with Clock Multiplexer Embedded

摘要：

A clock generator employing an adaptive bandwidth phase-locked loop (PLL) throughout wide output frequency range is presented. The PLL can operate from 150MHz to 2GHz under constant dynamic feature. In addition, an 8-bit clock multiplexer embedded in the output stage generates multiple glitches-free clocks while output frequency switching. Fabricated in a 65nm CMOS process, the clock generator provides the power consumption below 4.5mW under a 1.2V power supply. At 1-GHz frequency, the clock generator achieves rms and peak-to-peak jitter of 3.84ps and 31.02ps, respectively.

作者: Meng-Ting Tsai Yung-Chih Liang Yuan-Hua Chu Ching-Yuan Yang

作者单位: Information and Communication Laboratory, industrial Technology Research Institute, Hsinchu, Taiwan Information and Communication Laboratory, industrial Technology Research Institute, Hsinchu, Taiwan Department of Electrical Engineering. National Chung-Hsing University, Taichung, Taiwan

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 366-368

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）