A Low-Jitter and Low-Power Clock Generator

摘要：

This paper presents a phase-locked loop (PLL) for a clock generator in data communication system. The PLL exhibits simultaneously low jitter and low power consumption. Fully integrated loop filter simplifies the peripheral circuit. It has been fabricated using a 0.35 urn BiCMOS process, occupying 0.07 mm2 of silicon area. For a 50 MHz output frequency, the circuit features a 119 ps peak-to-peak jitter. At that frequency, the PLL consumes less than 6mW from a supply voltage of 3.3 V. The clock generator has been successfully applied in a receiver.

关键词： Phase-Locked Loop Ring Oscillator Low jitter Low power Clock Generator.

作者: Jiwei Huang Liang Tao Zhengpin Li

作者单位: Institute of RF-&OE IC, Southeast University, Nanjing 210096, China Guangzhou Runxin Information Tec Guangzhou Runxin Information Technology Company, Guangzhou 510663, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 385-387

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）