Active Clamp ESD Protection in Complementary BiCMOS Process

摘要：

A small footprint active clamp design with low voltage CMOS and high voltage BJT components in complementary BiCMOS process is proposed, analyzed by simulation and experimentally validated. The new clamp is composed from stacked NMOS driver to achieve appropriate voltage tolerance and power BJT. Both NPN and PNP- based versions of the clamp are compared to the stacked NMOS clamp.

作者: V.A. Vashchenko P.J. Hopper

作者单位: National Semiconductor Corp., 2900 Semiconductor Drive, Santa Clara, CA, 95052, USA

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 388-390

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）