An Area Efficient Multiplier Using Current-Mode Quaternary Logic Technique

摘要：

This paper proposes an area efficient 8x8 bit multiplier using current-mode quaternary logic technique. The multiplier is functionally partitioned into the following major sections: current-mode CMOS binary-to-quaternary encoder, current-mode quaternary logic full-adder block, and current-mode quaternaryto-binary decoder. The proposed multiplier has 2.4ns of propagation delay and 3.0mW of power consumption. Also, this multiplier can be adapted to binary system by the encoder and the decoder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25um standard CMOS technology with the supply voltage 2.5V.

作者: Jeong Beom Kim

作者单位: Dept. of Electronics Eng., Kangwon National University, R. of Korea

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 403-405

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）