A High-Performance Sample-and-Hold Circuit for 14-bit 125MS/s Pipelined ADC

摘要：

This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s and preserves 91dB SFDR and 82dB SNDR with the input frequency up to 160MHz. The designed circuit has been used in the front end of 14-bit 125MS/s pipelined ADC adapted for single-ended applications.

作者: Rui Zhang Hong-Hui Deng Yong-Sheng Yin Shang-Quan Liang Ming-Lun Gao

作者单位: Institute of VLSI Design, Hefei University of Technology, Hefei, 230009, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 424-426

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）