A Multi-bit Multiplying Digital-to-Analog Converter with Bi-directional overflow detection

摘要：

A design of a 3.5+1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. Two decision levels are added in the MDAC so that bidirectional overflow of the input signal can be detected. Bootstrap structure with a buffer is proposed to prevent the large bootstrap capacitance from loading the front stage circuit of the MDAC. A two-stage high gain and wide unity gain bandwidth opamp is designed. Simulation by Hspice based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows -84.23dB THD of the input sampling switches, 114dB openloop gain, 2.5GHz unity gain bandwidth of the op-amp, and 11-bit resolution settling of the output signal of the MDAC.

作者: Rui Zhang Yong-Sheng Yin Shang-Quan Liang Ming-Lun Gao

作者单位: Institute of VLSI Design, Hefei University of Technology, Hefei, 230009, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 427-429

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）