A Sub-sampling 3-bit 4GS/s Flash ADC in 0.13-μm CMOS

摘要：

A low-power single-channel sub-sampling 3-bit 4GS/s flash ADC in 0.13-μm CMOS is presented. Resistive averaging network and multi-stage interpolation technique are introduced for offset cancellation and power reduction, respectively. The comparator uses CML (current mode logic) blocks and pipelined structure to further enhance the speed of ADC. The simulation results reveal that the ENOB is 2.9 bit and ERBW is 4.8GHz. The ADC achieves a figure of merit of 0.58pJ/conversion-step.

作者: Yi Zhao Shenjie Wang Yajie Qin Zhiliang Hong

作者单位: State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 436-438

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）