Bandwidth-Efficient Architecture Design for Motion Compensation in H.264/AVC Decoder

摘要：

In this work, a Block-Clustering Based (BCB) method is proposed to reduce the memory access number of Motion Compensation (MC) in H.264/AVC Decoder. By grouping the possible 4x4 blocks within one Macroblock (MB) to share the loaded reference data, the memory access number can be significantly reduced around 70％ in average. Moreover, to reduce the precharge/active frequency during SDRAM accessing, a command-reordering method is adopted to achieve 60％ reduction in average. In our simulation, the total memory access number for processing one MB is less than 400 cycles. This method is scalable to different internal memory size used in MC hardware design.

作者: Chung-Fu Lin Chang-Chin Chung Yuan-Chieh Tsai Yu-Sen Ou

作者单位: Core Technology Development Division,No.5, Li-Hsin Rd. III, Hsinchu Science Park, Hsinchu City, Taiw Design Development Division, Faraday Technology Corporation,No.5, Li-Hsin Rd. III, Hsinchu Science P

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 445-447

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）