A 22mW 10-bit 150-MS/s Pipelined ADC in 1.2V 65nm CMOS

摘要：

This paper presents the low-power implementation of a 10-bit 150-MS/s pipelined analog-to-digital converter (ADC) in a standard 65 nm digital CMOS. The ADC removes the track-and-hold amplifier (THA) to reduce the power consumption. A 1.5 bit/stage architecture is used in the first stage to lower front-end design complexity. Three 2.5-bit stages are followed to reduce the stage number in the pipeline chain. Operational amplifiers (op-amps) sharing technique is used between consecutive stages for further power saving. A high swing continuous-time common mode feedback (CMFB) circuit is adopted in the op-amp design. Simulation results shows the proposed ADC achieves 9.8 ENOB with a 23 MHz input. The power consumption is 22 mW from a 1.2 V supply voltage. The active area is 640 μrn×470 μrn

作者: Jiacheng Wang Di Zhu Lele Guo Rui Jin Peiyuan Wan Pingfen Lin

作者单位: Beijing Embedded System Key Lab, Beijing University of Technology, Beijing 100124, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 454-456

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）