A high-speed, transmission delay stability comparator

摘要：

Based on the application of high-speed, highresolution A/D converter, this paper describes the design and implementation of a novel high-speed comparator. The comparator uses the high-speed, transmission delay stability technology, the autozero technology, and the cascade technology in order for the comparator to have the high-speed, highresolution, transmission delay stability features. Its performances are verified by a 14-bit 125MSPS pipelined A/D converter which is developed in 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 87 dB at an input clock of 125MHz with an input signal of 10MHz.

作者: Xingfa Huang Liang Li Zhengping Zhang Liang Chen

作者单位: National Labs of Analog Integrated Circuits, Chongqing 400060, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 457-459

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）