Design of an Ultra-low Power SAR ADC for Biomedical Applications

摘要：

In this paper, an ultra-low power 12-bit 2kS/s successive approximation register (SAR) analog-todigital converter (ADC) is presented. For power optimization, the voltage supply of the digital part is lowered, and the offset voltage of the latch is self-calibrated. Targeted for lower noise, a low kick-back noise latch is proposed. The chip was fabricated using 0.18μm 1P6M CMOS technology. The ADC achieves SNDR of 61.8dB and dissipates only 455nW, resulting in a figure of merit (FOM) of 220fJ/conversion-step. The ADC core occupies an active area of 674×639μm2.

作者: Hui Zhang Yajie Qin Siyu Yang Zhiliang Hong

作者单位: State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 460-462

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）