A 1V, 240 nW, 7 ppm/C,High PSRR CMOS Voltage Reference Circuit with Curvature-Compensation

摘要：

A low power voltage reference is implemented in a standard 0.18μm CMOS process. The temperature coefficient (TC) of 7 ppm/℃ is achieved in virtue of the output stage which consists of two transistors operating in subthreshold region and saturation region respectively. This kind of output stage is used to adjust the output voltage and compensate the curvature. The line sensitivity is 200 ppm/V in a supply voltage range of 1-3 V, and the power supply rejection ratio (PSSR) is -85 dB and -42 dB at 100Hz and 10 kHz, respectively. The maximum supply current is 240nA. The chip area is 0.016mm2.

作者: Pengpeng Yuan Dongmei Li Xin Wang Liyuan Liu Chun Zhang Zhihua Wang

作者单位: Institution of Microelectronics Electronic Engineering Department Tsinghua University Beijing, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 463-465

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）