A Ultra-Fast Load Regulation Capacitor-Free LDO With Advanced Capacitive-Coupling Feedforward Compensation
A low-power, capacitor-free low-dropout regulator (LDO) with Pseudo-Input stage feedforward compensation (PISFFC) is proposed in this paper. This novel FFC technique, employing the method of capacitive-coupling to provide large dynamic current for driving power transistor, is highly integrated, widely applicable and can provide ultra-fast load transient response. Compared to conventional slew rate enhancement(SRE) technique, the proposed technique is power-saving and can work at lower supply voltage. Moreover, with an additional lefthalf plane (LHP) zero generated by PISFFC. frequency compensation can be simpler and the unity-gainbandwidth (UGB) can be wider. A 50-mA LDO with a 0.2nF on-chip capacitor employed the proposed PISFFC has been implemented and simulated in a 0.13 μm CMOS process. Simulation results show that the LDO got low quiescent current(17uA), low-voltage operation ability(1.5V) and greatly improved transient response(output dips less than 170-mV in 0.1 us Switching time).
Hu Zhiming Zhou Ze-Kun Chen Yue Zhang Bo
State key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronics Science and Technology of China, Chengdu 610054, China
国际会议
上海
英文
482-484
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）