Low cost VLSI design of a flexible FFT processor

摘要：

In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from Ik to 32k FFT sizes is presented. The radix-22/23 based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum (N-1) memory words to get the FFT results. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements. A lk-32k flexible FFT core is implemented in the Altera FPGA, results show that our proposed scheme is suitable for applications where flexible large size FFT processor is needed such as digital video broadcasting, wireless networks etc.

作者: Jianing Su Zhenghao Lu

作者单位: Department of Electronics and Information Science, Soochow University, Suzhou, Jiangsu, 215006, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 488-490

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）