An Area Efficient Architecture of Resisting Long Echo Channel Estimation for DTMB System

摘要：

This paper proposed a VLSI architecture of resisting long echo channel estimation which is based on the algorithm proposed in 1. FFT module reusing and clock gating are used in order to reduce the hardware complexity and power consumption. The synthesis results show that the area can be reduced to only 65.5％ of architecture in which FFT modules are not be reused. And the power can also be reduced a lot (the Design Compiler result shows that the power of the scheme can reduced to 29.6％ of that before optimization).

关键词： DTMB channel estimation long echo area efficient VLSI.

作者: Yunlong Ge Xubin Chen Changsheng Zhou Yun Chen Yizhi Wang Xiaoyang Zeng

作者单位: State Key Lab of ASIC and System, Fudan University, Shanghai 201203, P.R.China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 497-499

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）