Analysis and Design of Low-Jitter Clock Driver for Wideband ADC

摘要：

The method of using small-signal model to analyze jitter of the clock driver caused by thermal noise is presented. Multi-stage quasi-infinite load differential amplifier structure to effectively achieve low clock jitter is proposed. With transient noise simulation, jitter in the clock driver can be calculated. Through testing the SNR of ADC, The jitter of the designed clock driver in this paper is below 260 fs so that it can be used in the high performance ADC.

作者: Long Cheng Haifeng Yang Lei Luo Junyan Ren

作者单位: State Key Laboratory of ASIC & System Microelectronic Science and Technology Innovation Platform, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 515-517

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）