A Novel Vector/SIMD Multiply-Accumulate Unit based on Reconfigurable Booth Array

摘要：

This paper presents a 32-bit vector multiplyaccumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32x32, one 32x16, two 16x16, four 8×8 bit signed/unsigned multiply-accumulate using Booth encoding algorithm and Wallace tree compressing. A reconfigurable Booth encoding array is implemented using 8×8 Booth unit as the basic element, and longer bit modes are obtained by combining these elements selectively. This MAC unit can also perform multiply between scalar and vector operands. 32-bit SIMD (Single Instruction Multiple Date) extended ISA (Instruction Set Architecture) and 3-stage pipeline are implemented for the MAC unit. The design is synthesized in 0.13μm SMIC technology under worst case condition, and the critical path of MAC is 2.5ns.

作者: Heng Quan Ruijin Xiao Kaidi You Xiaoyang Zeng Zhiyi Yu

作者单位: State Key Lab of ASIC and System, Fudan University, Shanghai 201203, P.R.China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 524-526

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）