Design and Verification of Logic Block Circuit in an SOI-Based FPGA

摘要：

A novel logic block circuit consisting of two multimode logic cells is proposed for the design of a tile-based FPGA fabricated with a 0.5um SOI-CMOS logic process. Each logic cell contains two 3-LUTs. The proposed 3-LUT based logic cell circuit increases logic density by about 12％ compared with a traditional 4-LLJT implementation. The logic block can be used in two functional modes: LUT mode and Distributed RAM mode, the latter of which can be configured in two modes: Single-Port RAM and DualPort RAM. Comparing with the published data on the CLB in Xilinx Spartan FPGA, the maximum LUT logic propagation delay has about 20％ improvement and the Distributed RAM average access time has about 21％ improvement.

作者: Xiaowei Han Stanley L. Chen Lihua Wu Yan Zhao Yan Li

作者单位: Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, P.R. China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 530-532

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）