An Optimized Tag Sorting Circuit in WFQ Scheduler Based on Leading Zero Counting

摘要：

The tag sorting circuit in Weighted Fair Queuing (WFQ) is crucial to the Quality of Service (QoS). In this paper, we present a kind of optimized hardware architecture for fast tag sorting, which consists of one-hot encoding and leading zero counting. The architecture is parallel and pipelining. It is implemented using FPGA technology. In comparison with the traditional comparator-tree-based architecture, it can improve the frequency by 15％ and reduce the area by 22％.

作者: Xiao-Ping Huang Xiao-Ya Fan Sheng-Bing Zhang Fan Zhang

作者单位: Computer School, Northwestern Polytechnical University, Xian 710072, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 533-535

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）