Design of an IPSec IP-Core for 10 Gigabit Ethernet Security Processor
Design of an IPSec (Internet Protocol Security) IPCore for 10 Gigabit Ethernet Security Processor is presented in this paper. The highest data throughput of one IPSec IP-Core can achieve 1.5Gbps. With parallel 8 IP-Cores, this design can achieve 10Gbps data process and fulfill a Gigabit Ethernet Security Processor requirement. The low power dissipation is also used in the IP-Core to reduce power dissipation.
Li Wang Yun Niu Liji Wu Xiangmin Zhang
National Laboratory for Information Science and Technology, Tsinghua Institute of Microelectronics, Tsinghua University, Beijing, 100084, China
国际会议
上海
英文
539-541
2010-11-01(万方平台首次上网日期,不代表论文的发表时间)