A Parallel Low Latency Bus on Chip for Packet Processing MPSoC

摘要：

In this paper an bus architecture combining crossbar switching with split transaction feature is presented for multiprocessor system on chip (MPSoC) in the packet processing application. The high throughput is achieved with crossbar bus topology and low bus latency is finished by split transaction buses which separate address bus from data one. Experimental results show that performance of the proposed architecture is improved up to 2.3 times than the one of the AHB buses and reduce communication latency about 45％ than the later. Moreover, the bus arbiter implementation has reasonable area and timing cost which make it suitable for high performance IP-packet or base-band processing.

作者: Pei-Jun Ma Pei-Yan Liu Kang Li You-Yang Zou Ai-Nv An Yan-Long Wang Yue Hao

作者单位: School of microelectronics of Xidian University, Xian, 710071, China School of microelectronics of Xidian niversity, Xian, 710071, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 545-547

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）