A 12-bit 50-MS/s Pipelined Analog-to-Digital Converter in 65nm CMOS
This paper presents a 12-bit 50-MS/s pipelined Analog-to-Digital Converter (ADC) in a 65-nm 1P7M CMOS process. A hybrid architecture is selected to make a trade-off between the power dissipation and performance of the ADC. For subsampling application, a wideband Sample and Hold Circuit (SHC) is proposed, including a high-linearity input switch and a twostage operational amplifier (opamp) with hybrid cascode compensation. Some optimization methods for design of Multiplying Digital-to-Analog Converter (MDAC) are also adopted. Simulation results show that the ADC maintains over 82 dB SFDR and 71 dB SNDR for input signal up to Nyquist range. The ADC consumes 53.8 mW at sampling rate of 50 MHz from 1.2-V supply voltage, and achieves a FOM value of 0.35 pJ/step.
Guanghua Shu Mingjun Fan Chen Shu Cheng Chen Ning Li Junyan Ren
State Key Laboratory of ASIC and System, Fudan University Cadence Design Systems, Shanghai 200001, China State Key Laboratory of ASIC and System, Fudan University Micro-/Nano-Electronics Innovation Platfor
国际会议
上海
英文
563-565
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）