Power-on Surge Current Minimization in an SOI-SRAM-Based FPGA

摘要：

A large and sudden current called surge current is always induced due to the momentary supply current through a low resistance path to ground when filed programmable gate array (FPGA) power on. This surge current will request the power supply of FPGA to source more current to meet this instantaneous demand or complicate the power management system of FPGA in order to succeed in powering up FPGA. Therefore, we describe and analyze the power-on surge current of FPGA in detail in this paper. According to the cause of power-on surge current, we modify the power-on sequence of FPGA, propose a novel SRAM cell embedded in the FPGA and add power routing pool to the FPGA, which have been implemented in an SRAM-Based FPGA, fabricated with a 0.5um SOI CMOS process. The experimental results of full chip power-on indicate that the power-on surge current of FPGA has been significantly reduced compared with Xilinx Spartan and Spartan II family devices.

作者: Lihua Wu Stanley L. Chen Xiaowei Han Yan Zhao Zhongli Liu Yan Li

作者单位: Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, P. R. China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 566-568

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）