A 10-bit 1MS/s Low Power SAR ADC for RSSI application

摘要：

A successive approximation register analog-to-digital converter(SAR ADC) targeted for use in RSSI(received signal strength indicator) is presented. The measured signal-to-noise-and-distortion ratios(SNDR) of the ADC is 53.95dB at lMS/s sampling rate with power consumption of 147.6 μW from 1.2-V supply voltage, thus the resulting FOM is 0.437pJ/conversion-step. The ADC is fabricated in a 0.13-μm technology.

作者: Zhen Zeng Chuan-Sheng Dong Xi Tan

作者单位: Department of Microelectronics, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 569-571

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）