Design of a Random Testing Circuit Based on LFSR for the External Memory Interface

摘要：

In the design of a SOC system, random test is gradually becoming an application for IP cores verification. This paper proposes a new random testing circuit based on LFSR to test the integrated EMIF IP core with restricted random verification methods. With the pseudo-random numbers generated by LFSR which works as a pseudo-random number generator, the testing circuit converts the numbers into test vectors which meet the AHB protocol. The test results indicate this circuit achieves random testing of the EMIF IP core.

作者: Jiajia Chen Zhaolin Li Qingwei Zheng Jianfei Ye Chipin Wei

作者单位: Institute of Microelectronics, Tsinghua University, Beijing 100084, China Research Institute of Information Technology, Tsinghua National Laboratory for Information Science a

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 578-580

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）