Timing Optimization for Deep Sub-micron Hierarchical Design

摘要：

In this paper, we use design planning method to partition a flat design based on SAED 90nm process technology into blocks and created interface logic models (ILMs) for each blocks. Using the hierarchical design including ILM, the runtime of the place optimization stage, clock optimization stage and route optimization stage is reduced to 28.8％, 27.7％ and 43％ relatively, meanwhile the boundary timing become more optimal which can also prove the timing accuracy of ILM.

作者: Shu-Xin Xu Li-Min Dong Xiao-Hong Peng

作者单位: VLSI & System laboratory, Beijing University of technology, Beijing, China Beijing, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 599-601

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）