Power Optimization for VLSI Circuits and Systems

摘要：

Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture level.

关键词： low power VLSI clocking system flip-flop

作者: Peiyi Zhao Zhongfeng Wang Guoqiang Hang

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 639-642

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）