SRAM Power Optimization with a Novel Circuit and Architectural Level Technique

摘要：

In this paper, an integrated 512KB SRAM architecture with low power circuit design is presented. An extra Z decoding circuit is introduced, which is combined with divided wordline/bitline scheme to reduce halfselected memory cells and thus dynamic power is decreased significantly. In circuit level, we utilize source biasing scheme to achieve leakage reduction and adopt an extra clamping diode in parallel with pull-down NMOS transistor to obtain data retention capability. Besides, power-gating method is proposed for wordline driver circuits. Simulation results on 55nm CMOS process indicates that leakage power and dynamic power can be saved by 66.7％ and 27.9％ respectively compared to conventional SRAM structure with performance penalty less than 3％.

作者: Chen Wu Li-Jun Zhang Yong Wang Jian-Bin Zheng

作者单位: The School of Electronics & Information Engineering, Soochow University, Suzhou 215006, China Aicest The School of Electronics & Information Engineering, Soochow University, Suzhou 215006, China Aicestar Technology Corp., Suzhou 215021, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 687-689

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）