A 8.5 GHz Phase Locked Loop with Split-Load Divider

摘要：

This paper presents a 8448MHz phase-locked loop (PLL) with a proposed divider implemented in 0.13 μm CMOS technology. Compared with conventional current mode logic (CML) divider, the proposed split-load divider presents wider operating frequency range and lower power dissipation. The ratio of the locking range over the center frequency is up to 70％ depending on the operating frequency. It consumes around 5mW power with 1.2V supply. The 8448 MHz PLL achieves phase noise of-92 dBc/Hz at frequency offsets of 100 kHz and has a reference spur of -56 dB with the second order passive low pass filter. The whole circuit (without test buffer) consumes only 13mA for a 1.2V power supply with die area of 0.9×1.3mm2.

作者: Haipeng Fu Deyun Cai Danfeng Chen Junyan Ren Wei Li Ning Li

作者单位: State Key Laboratory of ASIC and System, Micro-/Nano Science and Innovation Platform Fudan Universit State Key Laboratory of ASIC and System, Micro-/Nano Science and Innovation Platform Fudan Universit

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 770-772

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）