A New Membrane PSOI High Voltage Device with a Buried P+Layer

摘要：

A new Membrane PSOI High Voltage Device with a Buried P+ layer (MBP+ PSOI) is proposed. Breakdown voltage is only decided by lateral breakdown voltage because of the entire removing of silicon substrate under the drift region and breakdown voltage can be improved with increase of the length of the drift region. Introducing of P+ layer can effectively reduce specific on-resistance and silicon window results in alleviating significantly SHE. The simulation results show that breakdown voltage of MBP+ SOI is 734V and increases by 548V at Ld=37μm, ts=4um and t1=1μm, in comparison with that of SOI LDMOS. In contrast to Camsei SOI, the maximal surface temperature for MBP+ PSOI decreases by 34K and specific on-resistance reduces by about 44.8％.

作者: Xiao-ming Yang Bo Zhang Xiao-rong Luo

作者单位: School of Microelectronics and Solid State Electronics, University of Electronic Science and Technol School of Microelectronics and Solid State Electronics, University of Electronic Science and Technol

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 785-787

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）