FPGA Mapping Algorithm Based on Numerical Sequence Matching

摘要：

The FPGA logic block mapping algorithm described in this paper is based on numerical sequence matching. Numerical sequences are generated under certain rules to represent each functional circuit of the FPGAs logic block and the users input circuit. The mapping procedure is conducted by matching the sequence of the input circuits and the logic block. This algorithm can be applied for different types of LUT logic blocks. The complexity of this algorithm is O (n2), where n is the sum of the net nodes of the input circuit, which requires far less running time than the similar matching algorithms. A compact degree is also introduced in this paper, which shows a fine result of area saving.

关键词： FPGA Logic Block Mapping Algorithms Numerical Sequence Matching

作者: LiGuang Chen Yun Shao JinMei Lai

作者单位: ASIC & Systems State Key Lab, Fudan University 825 Zhangheng Rd., Shanghai, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 806-811

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）