Through-Silicon Via (TSV) Capacitance Modeling for 3D NoC Energy Consumption Estimation

摘要：

Three-Dimensional (3D) integration will take the next stage VLSI technology instead of 2D technology. In 3D chip, the electrical performances are much better than in 2D chip, for its short length. In this paper, an accurate energy consumption model of 3D ThroughSilicon-Via (TSV) is proposed for power estimation of 3D Network- on-Chip (NoC). The capacitance model of isolated TSV is analyzed in detail, and by comparing against Monte Carlo simulations in Silvaco. About 6.9％ and 10.1％ error of mathematic model exists to simulation results and measurement results. By integrating the model in NoC simulator, the energy consumption of network can be estimated quickly and accurately.

关键词： 3D TSV Network-on-Chip Energy Consumption

作者: Cai Jueping Jiang Peng Yao Lei Hao Yue Li Zan

作者单位: Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, Xidian University, Xian 710 State Key Laboratory of Integrated Services Networks, Xidian University, Xian 710071, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 815-817

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）