Mapper Design for an SOI-Based FPGA

摘要：

This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining FPGA architectural features and thus improve on the cluster occupancy of the logic resources. The result is proven in extensive test circuits used in our FPGA design. MCNC testbench comparison result is presented.

作者: Zhang Qianli Stanley L. Chen Yan Li Ming Li Liang Chen

作者单位: Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, P.R. China Tsinghua University, Beijing, 100083, P.R. China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 821-823

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）