Metal-Gate/High-K CMOS Scaling from Si to Ge at Small EOT

摘要：

Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~l nm EOT and low V, of -0.15 V are achieved in CMOS by using higher k gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-k/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO_2/Si universal mobility at an Eeffof 1 MV/cm.

作者: Albert Chin S. J. Wang C. H. Kuan F. S. Yeh W. B. Chen B. S. Shie K. C. Hsu P. C. Chen C. H. Cheng C. C. Chi Y. H. Wu K. S.Chaing-Liao

作者单位: Electronics Engineering Dept., Natl. Chiao Tung University, Hsinchu, Taiwan ROC Department of Electrical Engineering, Natl. Cheng Kung University, Tainan, Taiwan ROC Department of Electrical Engineering, Natl. Taiwan University, Taipei, Taiwan ROC Department of Electrical Engineering,Natl. Tsing Hua University, Hsinchu, Taiwan ROC Department of Physics,Natl. Tsing Hua University, Hsinchu, Taiwan ROC Department of Engineering & System Science,Natl. Tsing Hua University, Hsinchu, Taiwan ROC Electronics Engineering Dept., Natl. Chiao Tung University, Hsinchu, Taiwan ROC Department of Electr

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 836-839

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）