Patternable Low-k Material for GreenerSemiconductor Manufacturing
Increasing complexity and manufacturing costs, along with the fundamental limits of planar CMOS devices, threaten to slow down the historical pace of progress in the semiconductor industry. We report herein an efficient, low-cost, greener way to fabricate dualdamascene copper (Cu) on-chip interconnect or BackEnd-Of-the-Line (BEOL) structures using a novel multifunctional on-chip insulator, called a patternable low dielectric constant (1ow-k) dielectric material. We have developed a patternable 1ow-κ material that is compatible with 248 nm optical lithography and possesses electrical and mechanical properties similar to those of a conventional plasma enhanced chemical vapor deposition (PE CVD) deposited 1ow-k material. This k=2.7 patternable low-κ material is based on the industry standard SiCOH-based material platform. We have also successfully demonstrated single- and dual-damascene integration of this novel patternable 1ow-k dielectric material into advanced Cu BEOL. Furthermore, we have demonstrated multi-level integration of this patternable 1ow-k material at 45 nm node Cu BEOL fatwire levels with very high electrical yields using the current BEOL manufacturing infrastructure. Therefore, the patternable 1ow-k material concept is a promising technology for highly efficient, low-cost and greener semiconductor manufacturing.
Qinghuang Lin R. Kwong E. Liniger D. Neumayer J. Patel H. Shobha R.Sooriyakumaran S. Purushothaman T. Spooner R. Miller R. Allen S.T. Chen R. Wisnieff A. Nelson P. Brock S. Cohen B. Davis N. Fuller J.Gambino R. Kaplan
IBM Almaden Research Center, San Jose, CA 95120, USA IBM Systems and Technology Group, Hopewell Junction, NY 12533, USA IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, USA IBM Systems and Technology Group, Albany, NY 12203, USA IBM Systems and Technology Group, Essex Junction, VT 05452, USA
国际会议
上海
英文
975-978
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）