A Proposed High Performance High-k/Metal Gate CMOSFET Process with Optimism Strained Si cap/SiGe p-channel and Relaxed SiGe n-channel
We proposed a simple non-selective SiGe substrate high-k/metal gate CMOSFET process with optimized compressive-strained SiGe p-channel and relaxed SiGe n-channel. In this work, electron mobility can be recovered by relaxing compressive strain in SiGe nchannel using an appropriate thermal treatment to enhance Ge out-diffusion from SiGe substrate without degrade hole mobility in p-channel by an optimal thickness ratio of compressive-strained Si/SiGe substrate to suppress Ge out-diffusion. Post interfacial layer oxidation is proposed to repair oxygen-related defects in stack Hf-based oxides for reliability improvement. We achieved a high performance SiGe channel Hf-based high-k/TaC-based metal gate CMOSFET with stable VT, low C-V hysteresis (<5mV), good VT roll-off, lower gate leakage and better reliability, which can be a reference for 32nm and beyond device design.
Wen-Kuan Yeh C-Y. Chen C.-W. Hsu Y.-K. Fang
Department of Electrical Engineering, National University of Kaohsiung, Taiwan No.700, Kaohsiung Uni Institute of Electronic Engineering, National Cheng-Kung University
国际会议
上海
英文
979-981
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）